Analytical Current–Voltage Modeling and Analysis of the MFIS Gate-All-Around Transistor Featuring Negative-Capacitance

Recently, in accordance with the demand for development of low-power semiconductor devices, a negative capacitance field-effect-transistor (NC-FET) that integrates ferroelectric material into gate stack and utilizes capacitive behavior has been widely investigated. Furthermore, gate-all-around (GAA) architecture to reduce short-channel effect is expected be applied after Fin-FET technology. In this work, we proposed compact model describing current–voltage (I–V) relationships an NC GAA-FET interface trap effects first time, which simplified by taking proper approximation each operating region. This surface potential-based model, suitable evaluating I–V characteristics It was validated shows good agreement results implicit numerical calculations. addition, using explored electrical properties varying basic design parameters such as thickness (tfe), intermediate insulator (tox), silicon channel radius (R), densities (Net).